1. Field of the Invention
The present invention pertains to a semiconductor integrated circuit and a method for controlling thereof. In particular, the present invention pertains to a semiconductor integrated circuit including a circuit that saves and restores the internal state of the semiconductor integrated circuit and a method for controlling the semiconductor integrated circuit.
2. Description of the Related Art
Recently, a semiconductor integrated circuit having low power consumption functions of a standby function and a resume function is noted. Usually, when the power supply to the semiconductor integrated circuit is stopped, an internal state is lost excluding a nonvolatile memory. Therefore, it is necessary to hold the internal state in order to restart the operation of the circuit from the state immediately before the power supply of the circuit is stopped, when the power supply is restarted. For example, in Japanese Laid Open Patent Application (JP-A-Heisei 6-52070) a conventional integrated circuit is disclosed which saves and holds the internal state data held in registers in an external memory when the power supply is stopped. The conventional integrated circuit has a plurality of registers, a data saving unit, and a data restoring unit. The plurality of registers are connected to form a scan chain, and the data saving unit controls the plurality of registers to form the scan chain in a data save mode in response to an external signal, and reads the data held in each register outside through the formed scan chain. At this time, the data saving unit carries out series/parallel conversion on the internal state data into a data of predetermined bits width, and stored the data in a data protection memory through a data I/O unit. The data restoring unit controls the registers to form the scan chain in a data restoration mode in response to an external signal, and returns the saved data through the formed scan chain to the original registers. At this time, the data restoring unit reads the internal state data from the data protection memory through the data I/O unit, and converts the data of the predetermined bit width into the original internal state data, which are set in the registers through the scan chain.
Also, in US Laid Open Patent application (US 2004/0153762A1), a conventional data processing system is disclosed which includes a node circuit having one node or a plurality of nodes, a memory, a system bus, and a state saving controller. The node circuit is used to process data, and stores one data value or a plurality of data values that defines the state of the node circuit as a whole. The memory stores the data. The system bus is connected to the node circuit and the memory, and transmits multiple bit data word between the node circuit and the memory in response to a memory transfer request supplied to the system bus during a usual processing operation of the node circuit and the memory. The state saving controller connects the node circuit and the system bus in response to a save trigger, reads the data values that defines the state of the node circuit from the node or the plurality of nodes, and generates a sequence of a memory write request on the system bus. Furthermore, the state saving controller writes the plurality of states of the multiple bit data word that shows the data value in the memory, and then can restore the state of the node circuit by using the plurality of states of the multiple bit data words. Moreover, a relating technique is disclosed in US Laid Open Patent Publication (US 2005/0149799A).
As described above, the scan chain is composed of a plurality of registers connected in series. Therefore, it would take a long time to save and restore in serial all the data held in the registers. Moreover, it is necessary to start a memory read sequence and a memory write sequence after being granted the system bus, in order to read/write the internal node data from/to the memory through the system bus. Therefore, the saving and restoring time of the internal state still becomes so long.